In
processing, the phenomenon when a planned
instruction cannot
execute in the proper
clock cycle, or clock tick, because the
hardware it is running on cannot support the combination of instructions that are set to execute in the given clock cycle, causing resource conflicts. For example, a structural hazard would occur if a processor tried to use the same memory
port for both instructions and data. Structural hazards commonly are overcome by
pipelining MIPS instruction sets.
